A Power Model Combined Of Architectural Level And Gate Level For Multicore Processors

Power estimations are the basis of power optimizations. Recently, powerdissipation has become possibly the most critical design constraint of modern andfuture processors, which highlights the role of power estimations in processor design.Single-core processor era has passed; chip multiprocessors inexorably become themainstream processors. How to establish an accurate power model for chipmultiprocessors becomes a hot topic in current academic research.According to the different design phases of chips, estimation methods of overallpower consumption is divided into four categories. Due to their distinctive features,architecture-level and gate-level power estimation methods get the most attention.However, as the transformation of processor design method and the progress of themanufacturing process, architecture-level power estimation methods have been unableto accurately estimate the power of processors. And gate-level power estimationmethods cannot make timely evaluation for power in design flow early due to the needof specific circuit information. For these shortcomings, a power estimation methodcombined of architecture-level and gate-level for multicore processors is proposed inthis paper. The method not only inherits the speed of the architecture-level powerestimation method, but also improves its accuracy. At the meantime, it has someflexibility. Specific research is as follows:First of all, multi-core processors are divided at the circuit level and architecturallevel, respectively. Circuit-level division is based on the power characteristics ofcircuits, and for each type to choose appropriate power estimation method.Architecture-level division is base on the function of blocks, and each block ismapped to one of these circuit types.Then, the power of blocks which are suitable for using gate-level powerestimation methods are calculated in accordance with the integrated circuit designprocess. The process starts from the design of RTL codes of blocks, and includessynthesis, placement, routing and power analysis. After done these steps, gate-levelpower is got. The architectural parameters and structure design of blocks are takeninto consideration in the design of their RTL codes, making it covers all of structuresof each block as far as possible. And these power numbers are made in the form of alookup table.Finally, McPAT which is an architectural level power simulator is modified to integrate the power lookup table; Gem5which is a performance simulator is modifiedto record the run time statistics.Experimental results show that compared with the architectural level powersimulator, our power estimation method can more accurately assess the powerconsumption.