The Research And Implementation Of High Efficient Video Coding System

With the rapid development in the area of communication technology and computer technology, digital video plays a more and more important role in information society. Image/Video transmission and processing have become hot focus of study in the field of industry and academe. ISO and ITU-T have put forward some advanced, standards. Common people enjoy the convenience made by the popularization of these standards, while the development of Very Large Scale Integrate circuit (VLSI) and Programmable Logic Device (such as FPGA etc.) makes real-time video compression and transportation possible. After having studied a set of MPEG standards proposed by ISO, which are all international standards of multimedia compression system, we designed and implemented MPEG-4 encoding system on ASP level by FPGA.This dissertation presents the achievement we have obtained about several issues in video coding and its hardware implementation. First of all, the history and actuality of image compression technology and its application are introduced. Some popular video coding standards including H.261, H.263, MPEG-1, MPEG-2, MPEG-4 and MPEG-7 are discussed briefly. Then some key techniques in MPEG-2 and MPEG-4 recommendations are studied and compared in detail, including motion estimation, motion compensation, discrete cosine transform, inverse discrete cosine transform, variable length coding and layered description of picture and code stream. Consequently based on these studies, an MPEG-4 ASP video coding system is implemented with now-poplar SoC technology, and the network transmission function is also achieved in this system. We do this by adopting FPGA plus ARM. In the system, the source coding and error correction are fulfilled by FPGA, and network protocols are fulfilled in MCU unit. This system realizes real-time video coding and transmission when the input picture resolution is 352X288 and its frame rate is 25 frames pre second. The performance of this coding system is satisfying in the output bit rate of 384kbps.Most of all, we give a feasible network transmission model for video associated with RTP/RTCP protocols. In the course of implementation on hardware, SDRAM is adopted to design a reasonable and practical data manipulation scheme for MPEG-4 data stream. The system minimizes the resource requirements while meeting a definite function target. Besides, on the basis of study on rate control of TMN8, we also designed the section of rate control of this system in the way of both hardware and software. Some incentive experiments demonstrate the system with stable and good performances.In the long run, h.264 recommendation will rapidly flourish with accompanied by the progress of MPEG-4. Because both of them are similarly proposed to aim at low rate applications, an analogical coding system associated with network transmission for h.264 can be built, which also on FPGA plus ARM. We will further study the system by transplanting RTOS in ARM, which makes the system more general and more applicable.