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The Optimization And Simulation Of HDTV Software Video Decoding Based On TMS320C64xDSP

Posted on:2005-10-01Degree:MasterType:Thesis
Country:ChinaCandidate:J LiFull Text:PDF
GTID:2168360122487583Subject:Signal and Information Processing
Abstract/Summary:PDF Full Text Request
Digital audio and video processing technology is the engine of multimedia application in recent years. Audio and video compression is the core technology of digital audio and video processing. Compression algorithm is complex and has much operation. To compress video and audio signal efficiently and in real time is a chiefly problem in multimedia technology.From analog black and white television, analog color television to digital television, TV industry has great change. HDTV (High-Definition TV) supply better image and sound. Receiver or Set-top box has a great potential market. The implementation of digital TV Set-top box has two methods. One is implemented by ASIC, such as STi7020, the other is by general purpose chip, including FPGA and DSP. ASIC has strong function, advanced technology and low price. Now when decoding HDTV video stream, all the decoders are implemented by ASIC. But we have no intellectual property by using ASIC, only if the standards have been changed, the ASIC must be fallen into disuse. We can overcome these shortcomings by using general purpose chip. To use FPGA is based on hardware, it is difficult to implement the system by using this method. While to use DSP is based on software, we can make use of DSP to development Set-top box if only DSP has enough operation ability.The thesis designs a HDTV video software decoder based on TMS320C64x general purpose DSP. Considering the structure of TMS320C64x, several optimizations have been made. Variable length decoding, IDCT and motion compensation are coded in parallel assemble language. By evaluating the object code on TMS320C64x software simulator, we can make several conclusions: 1) The CPU cycles consumed after assemble optimization is one seventh of the cycles before optimization; 2) After assemble optimization, this video software decoder only consumes 228.8MHz CPU cycles; 3) When decoding hi-definition video bit-stream, about 1GHz CPU cycles will be consumed. This research is very important for implementing a HDTV video decoder by using general purpose DSP. It promotes the development of DSP usage in consumer electronic application field.Last, the thesis design the IMDCT software of AC-3 audio decoder based on float DSP TMS320C6701, the result is that TMS320C6701 can decode audio signal and control the system in real time.
Keywords/Search Tags:Digital TV, HDTV, DSP, MPEG-2, AC-3, TMS320C64x, TMS320C6701
PDF Full Text Request
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