Research And Circuits Design On System Data Transfer Standard Protocol

It is the fast development of IC that forces the advancing of SoC and computer system,and as a necessary department of which, the data transfer is undergoing a bigevolution.In order to unify the interface of data transfer, the industry made a series of standardprotocols. These protocols are also being developed as the improvement of thesystem's performance.The cases of data transfer are different at the different level in the system. It isreflected in the different standard protocols in which the behavior of data transfer isdifferent.It is not enough that we only talk about standard protocols, because they are onlydefinitions and rules on the paper. The real standard protocols must be reflected in thereal circuit. Being different from the pure logic circuit design, the data transfer controlcircuit is not only responsible for control the data transfer and make it follow thestandard protocol, but also responsible for connect the internal circuit with theexternal bus interface and make them work together properly.There are some differences on the matching between the internal circuit clock and theexternal circuit clock at the different data transfer level. Some belong to twosynchronous clock domains' matching, while some belong to two asynchronous clockdomains' matching. This will bring huge differences on the circuit implementation,but it can't be seen on the standard protocol level.As the improvement of the data transfer's clock frequency, the conventional parallelbus are becoming more and more uncompetitive. So the new technology which is baseon serial transfer occurs. The clock frequency of serial data transfer is not infected bythe data signal skew, so it can be improved dramatically. But this can bring a series ofproblems, such as high frequency circuit design, compensation of clock mismatch.Because the data transfer standard protocol includes all kinds of exception handling inthe real runtime, it is worthy to researching and discussing how to verify data transfercontrol circuit to achieve highest test coverage.