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Research On The Defects Of 55nm Copper Interconnect Technology

Posted on:2020-01-25Degree:MasterType:Thesis
Country:ChinaCandidate:H GuoFull Text:PDF
GTID:2518306503974169Subject:IC Engineering
Abstract/Summary:PDF Full Text Request
As the technology nodes continue to decrease according to Moore's Law,the feature size is further reduced.The BEOL process generally introduces multilayer copper interconnect processes and low dielectric materials to reduce the impact of RC delay,which also make the processes complicated.The continuous development of integrated circuits in the direction of high density makes the chip's tolerance to defects become lower and lower,and the defect problem becomes one of the main reasons for the loss of yield.In this paper,the main systematic defects of copper interconnect process at 55 nm platform in the company are studied in depth,and an effective improvement scheme is proposed.In order to solve the problem of peeling defects in wafer edge caused by the thin film process,the interference caused by Cu hillock is solved by reasonable selection and matching of dark field defect detection polarization filtering and Fourier filtering technology.The number of defects was reduced by 83% by adding wet cleaning on the backside of wafer.The benchmark process conditions were optimized and the lithography leveling data range was improved by95% after 10 times of cleanings using the new process conditions.In view of the void defects caused by the electroplating copper process,bright field after NDC DEP has been introduced to solve the interference caused by copper crystallization.The experimental data showed that the thinner barrier layer was combined with the thicker seed layer to meet the step coverage requirements.The high current density stability and stronger additives can increase the copper filling capacity.The defect was improved by 67% by using the new process conditions.In order to solve the defocusing in wafer edge caused by copper grinding process,the grid pattern density repair method was adopted to repair the layout hotspot,and the CMP process window was expanded.With the optimization of the grinding head pressure parameters,the number of defects in the new process conditions improved by 83%.The research and solution of the above technical problems not only improved the yield of products,but also further improved the quality of the55 nm process platform.The improvement directions and solutions proposed in the problem research also provide valuable information for the research and development of 28 nm process in my company.
Keywords/Search Tags:Copper Interconnect, Low-k dielectric material, thin film deposition, Electro copper plating, Chemical Mechanical Polishing, defect reduction
PDF Full Text Request
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