Strategies Of RC Delay Reduction In45Nm BEOL Technology

As the decreasing of integrated circuit critical dimension and theincreasing integration density, according to the device scaled down the basicprinciples of device CD shrink leading to current increased density, andmetal systems most severely affected, with the interconnect cross-sectionalarea decreases, the interconnect layers increases, leading to increased RCtime. At the0.25um technology, the interconnect RC time constant timedelay has been caused by the delay and the transistor itself, rather, when theCD further reduce，the time delay will become prominent, especially to the45/40nm.BEOL interconnect delay related with interconnect line resistance Rand dielectric capacitance C, copper are used as the interconnect metalmaterials after0.18um technology, BEOL copper processing are mainlysingle-and double-Damascus process. In addition, a low k dielectric layeralso effectively reduce the capacitance, the current mainstream blackdiamond material is used, the introduction of BLOk film as a low-kmaterial and the isolation between metal layers.To solve45/40nm RC delay, when there is no connection to find amore low-resistance metal material and lower k values dielectric layermaterial, at the end of this article describes the strategy of reducing R andC, can do copper Internet diffusion barrier layer thickness experiment toreduce the connection resistance, and dielectric layers of differentthickness matched to reduce the equivalent capacitance. From45nm BEOLbarrier layer and the insulating dielectric layer of low-k analysis, provedthe diffusion barrier layer reduces5A, a2%decrease in electricalresistance, dielectric layer increases200A, a6%reduction in capacitance, overall RC delay decreased by8%. Electromigration reliability, yield ofthe wafers can also be guaranteed.