Improvement On Void Defects In Vias Of Dual Damascene Copper Plating Based On 40nm Technology

With scaling-down of the semiconductor device,metal interconnect becomes more and more important for final qualities,such as reliability,RC delay and energy consumption.Since 130 nm process technology,copper interconnection has taken the place of aluminum for its perfect performances including RC delay and anti-electromigration.Electrical copper plate(ECP)is one of the most important process.For 40 nm process technology,the diameter of the smallest via is just about 90 nm.Void defects,which are difficult to be detected after ECP even after CMP(Chemical Mechanical Polishing)with defect scanner,were much easily formed in via during ECP.Only using failure analysis after final WAT test,yield test or reliability test these void defects can be detected.That results in the wast of resource.That finding the root cause of the void defects and solving it can improve the yield of chips and reduce the cost of manufacturing.The mechanism of this voids defect during ECP is studied in this thesis.Analyzed the defect map it was found that these void defects were mainly located on a side of the wafer.Combining with special entry of wafer in ECP,test of adjusting the speed of clamshell drop into solution to change the entry spot of the wafer was designed to get conclusion that void defect came from the process of ECP.Some experiments were designed to study the relationship between different stages of solution life and defects.It was found that at the end of the maintenance cycle,there were more impurities in the solution,which was easy to be brought to the wafer and copper plating,resulting in pits defects.The ratio of additive concentration in solution was studied,and a variety of ratios were designed.It is concluded that in extreme cases,when the ratio of accelerator and suppressor is more than 15:1,the via will be sealed ahead of time in the electroplating process,resulting in void defects.When the wafer is immersed in the solution at the beginning of copper plating,the corrosion of the acid solution to the copper seed layer occurs at the same time as the electroplating at the beginning of circuit conduction.An attempt is made to increase the current at the first step of electroplating to strengthen the electroplating effect and weaken the corrosion effect.The results show that the improvement is significant but not thorough when the current at the first step is adjusted to 11 A.However,some devices on the wafer were found to be damaged by arc discharge when the current continues to increase to 15 A.The process window is too small.According to the characteristics that the copper seed layer may be oxidized and corroded before copper plating and the self-annealing of the copper film after copper plating,experiments with different waiting times are designed.It is concluded that the copper seed layer prepared by magnetron sputtering should start copper plating as early as possible to avoid oxidative corrosion,while the start of copper CMP within a safe range of one to ten hours after copper plating can reduce the number of defects to the lowest and efficient way.In mass production semiconductor manufacturing factory,not every lot can run one step by one step immediately for cycle time bottle neck,so the waiting time is inevitable.The nitrogen filling device is introduced to reduce the contact of the wafer with oxygen during the waiting time so as to reduce the oxidation reaction of the copper seed layer.The first step current can improve the corrosion reaction when the wafer is immersed in the solution,but the effect is limited.On this basis,the concept of pulse current is introduced,and the high current in a short time can reach a balance between corrosion and electroplating.The CMP process should be completed within ten hours after copper plating,otherwise the self annealing of copper metal will continue,and the voids will gradually gather,which will affect the properties of the final copper wire,so the redundant copper should be removed as early as possible.Through the above optimization process,the number of defects in the40 nm product has been reduced from an average of 110 ea.to less than 50 ea.,and the number of void defects is basically zero,and the yield and reliability have also been improved by 0.5%.