Study On The Stress During Formation Of Vertical Copper Interconnection

In recent years,with the rapid development of electronic industry,integrated circuit(IC),the proportion of transistors is shrinking.However,shrinking has reached the nanoscale physical limits of the semiconductor size..It is still a challenge to manufacture semiconductors with higher density and higher integration.To continue"Moore's law",3D packaging chip stack stereo type gradually became the optimal choice for researchers.Through vertical copper interconnect technology can stack up chips ando realize the higher density of integrated circuits,integrated equipment lower power.It has won the acceptance by many researchers.However,the stress issue in copper interconnection will strongly impact the manufacturing process,leading to the failure of copper interconnection,affecting the reliability of the electronic product hazard.The study of stress in 3D electronic packaging is important for the reliability performance and pervasive application of electronic packaging products.We focus on the electroplated stress and thermal stress in copper interconnection technology.In this paper,we chose methyl sulfonate copper plating system as the basis of plating solution system which has a broader electrodeposition process window and is more environmental protection and efficient.The research include:the influence of additives(accelerator-inhibitors-leveling agent system)on the electrodeposition of copper stress.Using first principles and density functional calculation method,we analyze the adsorption performance of additives.Using ANSYS finite element simulation software and EBSD analysis software,we analyze the influence of different temperature thermal treatment on the the stress and organizational structure of copper in TSV.1.Study on the influence of additives in bath on the coating copper internal stress.The additives include the accelerator(SPS),the inhibitor(PEG)and leveling agent(JGB,2-MP and 2-ABT).The analysis includes internal stress,texture,surface morphology,grain size effects and electrochemical behavior.The results reveal:the additives in solution strongly connect with the stress of electroplated copper.The influence of accelerating agent SPS on the electroplated copper stress is compressive stress The influence of inhibitors PEG on electroplated copper stress is tensile stress.And the stress almost does not change with concentration of additive.The influence of leveler on the electroplated copper stress is more complicated:2-MP makes the electroplated copper have tensile stress;2-ABT makes the electroplated copper have compressive stress;JGB makes the electroplated copper have tensile or compressive stress.This special ability of leveller is suitable for using in the method that adjusting the stress of electroplated copper stress through changing additives.2.Study on the influence of leveller(2-MP and 2-ABT)in solution on electroplated copper in self annealing.Using density functional and first principles calculation method,we analyze quantum chemical properties of the 2-MP and 2-ABT and adsorption performance of them on the crystal face(111),(200)and(220)of copper through molecular dynamics.2-MP makes the properties(stress,texture and grain size)of electroplated copper stable in the self annealing.On the contrary,2-ABT makes the properties change in the self annealing.The quantum chemical calculation results show:the adsorption ability of 2-MP is stronger than 2-ABT,especially the S in 2-MP.The XPS results also prove that Cu(2-MP)has much more S impurity are entrapped on the deposited copper than Cu(2-ABT).The inhibition of 2-MP and high concentration of impurity entrapped in copper prevent the grain growth possibly resulting in the microstructure and stress stabilization in the electroplated copper film during the self-annealing,while the acceleration of 2-ABT and low concentration of impurity entrapped in copper brings both variations.3.Study on the influence of different temperature thermal treatment on the TSV(Through Silicon Via)with 100?m×13?m depth-to-width ratio.As the difference of the coefficient of thermal expansion of copper and silicon,plastic deformation of copper occurs in 400°C annealing treatment.The finite element modelling results show:in thermal treatment,the distribution of thermal stress in TSV is mainly on the interface of copper and silicon and especially on the top of the via.The tensile stress of electroplated copper is good for remitting the thermal stress,but can't reduce the highest thermal stress value.The EBSD results show:the grains with softest orientation reduce and the distribution of coherent?3that has the lowest energy increases in copper after 400°C thermal treatment.These results indicate the copper in TSV has the stronger ability to resist plastic deformation after400°C thermal treatment.The TSV after 400°C annealing treatment is better than that after 300°C thermal treatment in IC manufacture.According to these results,high temperature around 400 ~oC thermal treatment followed by CMP might solve the problem of extrusion during TSV manufacture process after via filling.