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Design And Study Of New Structures For MOSFET Power Devices

Posted on:2022-09-14Degree:MasterType:Thesis
Country:ChinaCandidate:T B DangFull Text:PDF
GTID:2518306554970689Subject:Master of Engineering
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MOSFET power devices have the advantages of simple driving method,easy integration,easy parallel connection,high input impedance and fast switching response,which are widely used in various fields such as transportation,life entertainment and military aviation.However,due to the paradoxical relationship between the specific on-state resistance(Ron,sp)and breakdown voltage(BV)of 2.5 times,the on-state resistance increases significantly with the increase of breakdown voltage,which seriously limits the application of MOSFETs in high-voltage and high-power fields.This paper revolves around how to improve the contradictory relationship between Ron,sp and BV in transverse MOSFET power devices and how to reduce the effect of curvature effect and increase the breakdown voltage of MOSFET power devices.Three new MOSFET power device structures are proposed:(1)An enhanced depletion n-layer stacked LDMOS device structure.This structure consists of multiple independent LDMOS devices stacked together,and the multiple current paths formed by the stack greatly increase the on-state current of the device.In addition,the current in each current path works independently without interfering with each other under the action of each LDMOS substrate.In addition,the addition of a P-buried layer and P/N-top region in the device can effectively improve the electric field crowding phenomenon near the source drain of the device,thus increasing the breakdown voltage of the device.Simulation results show that the breakdown voltage of 2-layer stacked LDMOS is 356 V and the specific on-resistance is 13.56 m(?)·cm2,which is 26%and 71%better than that of C-LDMOS,respectively.Moreover,as the number of stacked layers increases,the specific on-resistance of n-layer stacked LDMOS devices will tend to be 1/n of that of conventional structures.(2)A slot-gate LDMOS with multi-buried layer modulation,which reduces the specific on-resistance of the device by adding three P-type buried layers of different lengths in the drift region and increasing the doping concentration in the drift region by using the depletion effect of the buried layers on the drift region.Moreover,the buried layer generates new electric field peaks inside the device,which improves the electric field distribution inside the device and thus improves the voltage withstand characteristics.Simulation results show that the structure has a breakdown voltage of 678 V at turn-off and a specific on-resistance of 49.4 m(?)·cm2 at on-resistance,which are 104%and 56%improvements,respectively,compared with the conventional structure.(3)A termination structure with multiple shallow dielectric slots.The structure incorporates multiple equally spaced shallow dielectric slots in the terminal area,so it can generate multiple electric field peaks on the surface of the terminal area,thus optimizing the surface electric field in the terminal area and improving the BV value.The simulation results show that the breakdown voltage of this structure is 716 V,which is 119%better than the conventional protection ring technique and reaches 95%of the cell,and the terminal length is 103?m,which is 11%better than the equal height shallow slot terminal structure with the same parameters.
Keywords/Search Tags:MOSFET, Breakdown voltage, Specific on-resistance, Termination techniques, LDMOS, VDMOS
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