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An integrated circuit reliability model and its applicability towards improving programmable logic device reliability

Posted on:1993-09-08Degree:Ph.DType:Dissertation
University:University of Missouri - RollaCandidate:Paunicka, James LouisFull Text:PDF
GTID:1478390014997511Subject:Electrical engineering
Abstract/Summary:
This dissertation describes a new way to model the lifetime of a digital integrated circuit. The focus of the modelling effort is aimed at determining whether on-chip redundancy enhances IC (integrated circuit) reliability. Existing models proposed for this purpose have been difficult to use because there are no sources of data for their input parameters; an example of such a parameter is an exponential failure rate for some arbitrary section of an IC's semiconductor chip.;The new model uses input parameters which are readily available for the world's most comprehensive databases. The modelling method assumes that a single temporal Poisson process governs the arrival of faults within an IC. That is, the IC follows the exponential failure law. Other existing models, on the other hand, consider an arbitrary number of Poisson processes simultaneously occurring within an IC. The failure rate for the new model is taken from MIL-HDBK-217, a recognized authority in electronic component failure rate modelling.;Dynamically arriving faults are mixed with a spatial fault location probability in the model to determine whether the faults are tolerated by on-chip redundant logic. Specific on-chip redundancy architectures are modeled in detail.;The use of programmable logic for enhancing electronic system reliability and maintainability is explored. It is suggested that programmable logic can drive a new paradigm in on-chip redundancy. That is, the use of on-chip redundancy for random logic structures is no longer out of the question from a yield-driven economic standpoint. The use of programmable logic, with its guaranteed yield, allows any type of redundancy to be used on a chip without worries about yield. This use of redundancy, with all its extra gates, should not be used, though, unless it can be shown that IC reliability will actually increase. The new model provides a way to predict these possible reliability increases.
Keywords/Search Tags:Model, Integrated circuit, Reliability, Programmable logic, New, On-chip redundancy
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