Study Of Fault Tolerance Method Based On Redundancy Transmission For Network On Chip Soft Error

As semiconductor process technology scales, the new approach of network on chip (NoC) develops fast. At the same time, it also brings tremendous challenges to NoC design, mainly affected by the manufacturing process for the NoC system, signal noise and crosstalk, electromagnetic interference, electron mobility and other factors, which result in more and more permanent errors and soft errors. System-level fault tolerance is a proper and efficient working method to ensure that the chip.This paper presents a variety of transmission methods based on data redundancy to improve the reliability of NoC communication. Taking into account the different impact of different errors, the error are classified. More attention is paid to errors that cause deadlock and network freeze and strengthen the protection in this situation, using a triple-mode redundancy program; as control information being protected, we consider the protection of the transmission of data. This paper uses various redundant programs, designed a fault injection model based on the soft error in NoC. We build the platform and simulate all the programs. The results show that when faults are injected in the link and the buffer (fault rate less than ), the system's entire transmission reliability is more than 99.99 percent. Under 0.0001 error injection rate, the system reliability achieves more than 99.999 percent. The fault-tolerant solutions presented in this paper well protect the on-chip network data transmission reliability.