Study On Fault And Reliability Test Of Memory Chip

Due to its excellent performance, memory has been widely used in some high and new technology industries like data processing, mobile communication, embedded system and intelligent equipment. Memory capacity varies from a few KB in 1980s to several TB now. Especially, the trend of memory capacity expansion is even greater in recent years. At present, the function of memory is quite rich, which can be applied in various high and new technology, and has greatly enriched the function of electronic products.Great changes have taken place in the access speed, capacity, and function of memory. It’s no doubt that the development of these high quality memory puts forward higher requirements towards its test verification. These high-performance memory has a large capacity,so when the density of the memory cells increases, the probability of interference between the cells will increase in the meanwhile, which poses a higher requirement to ensure the reliability of the memory.Above all, this paper analyzes the development status of domestic and foreign memory and integrated circuit testing system, researching on the test technology of NAND flash memory and semiconductor memory fault model, analyzing the memory full "1", full"0" pattern test algorithm and parity graphics detection method, as well as proposes a graphic combination of these two methods-walking test algorithm based on the optimization. In this paper, the ATE test system is used to test the DC/AC parameters of the target chip NAND flash memory.In the end, the reliability analysis technology of integrated circuit is introduced, and the reliability of the memory durability is analyzed with the test data. Besides,under the condition of reading and writing, the paper studies the change of threshold voltage of the memory cell. The paper tested flash memory DC/AC parameters through analyzing the working principle of NAND flash memory, and also puts forward the improved marching-walking graph algorithms, which will make a full coverage of the test of memory unit, as well as optimizes the reliability technology of NAND flash memory. Furthermore, the paper analyzes and researches the relationship between the voltage stress condition and the reliability of the storage unit in the light of the test data.