Manufacturing test simulator for chips

This dissertation presents Manufacturing Test SIMulator for Chips(MTSIM-C). MTSIM-C is a concurrent engineering tool to predict the manufacturing test cost, yield, and quality of an integrated circuit(IC) in the early stage of the design cycle. MTSIM-C predicts the chip manufacturing yield, the fault coverage, and the testing cost for a given manufacturing environmental information. MTSIM-C helps chip manufacturers to identify future manufacturing problems in the early stage of the design cycle, and can help to avoid costly DFT mistakes.;A board and Multi-Chip Module(MCM) level manufacturing test simulator, MTSIM-B [1], has been developed to analyze the board and MCM level manufacturing test. The purpose of MTSIM-C is to develop a simulator with similar architecture as MTSIM-B, but targeting chip level manufacturing test. Several manufacturing parameters have to be predicted in order to select the optimum test strategy. The manufacturing parameters include the chip yield and the fault coverages of various test methodologies are estimated. Once the chip yield and the fault coverage are estimated, the chip manufacturing test cost can be estimated.;The difficulty of predicting chip yield in the early stage of the design cycle is due to the fact that chip layout is often not available at the time. Therefore, the first objective of MTSIM-C is to develop a yield model which predicts chip yield without detailed netlist or layout information. A chip yield can be estimated using defect density and sensitive area. A sensitive area model was developed to predict chip's sensitive area based on circuit information such as gate count, unique signal net count, and circuit type (random logic, memory, datapath). The chip yield can be projected by incorporating the sensitive area and the fabrication defect density using the available yield equations. Our second objective is to develop a set of fault coverage models. The goal of developing the fault coverage models is to achieve the first order approximation of fault coverage under different Design for Testability (DFT) techniques. The fault coverage model obtained from this research is an exponentially decaying function with three parameters, which include the fault coverage upper bound, UB, the fault coverage lower bound, LB, and the rate of fault coverage change, alpha. The fault coverages using three DFT techniques, which include no DFT, Scan, Iddq testing, are predicted using circuit information, such as gate count, IO count, and FF count. These parameters are often readily available at the early stage of the design cycle. Finally, a chip manufacturing test cost model, which incorporates the yield and fault coverage information with other manufacturing environmental information, is developed to predict the chip testing cost.