Study On IC's Soft Faults And Related Techniques Of Functional Yield

This thesis aims at discussing the model of manufacturing defects, the principles of soft and hard faults induced by manufacturing defects, the effects of soft fault on circuit reliability and yield and the relationship between yield loss and reliability decrease caused by manufacturing defects.The author's main contributions are as following:Reliability and yield are two significant factors to semiconductor manufacture. Based on the principles of the manufacturability engineering, the thesis discusses the effects of the manufacturing defect on the functional yield, parametric yield and the reliability for ICS, and abstracts geometric models from actual chips. At last, the model of defect size distribution and the model of soft and hard faults caused by defects is given.Electromigration effect is still a dominating failure mechanism of interconnect for deep submicron and ultra-deep submicron scale. Based on the model of the interconnect failure, taking the existence of defect into account, the influence of the open soft fault on the interconnect reliability is deeply studied, and a new lifetime model of interconnect is presented.Calculation of critical area is the base of yield prediction. Applying the theory of polygon expanding and shrinking, a new critical area calculation method for soft and hard faults is given. A total formula is presented by dividing VLSI interconnects into two parts, contacting and conducting path, to calculate its critical area. Finally the effect of hard and soft fault of different size defect on circuits is given by calculating soft fault area of a 4x4 shift register. The result shows that the soft and hard faults will have different significance to the performance of circuits at a wide range of defect size.The relationship between yield and reliability is concerned for a long time. With the principle of defect occurrence, a new accurate discrete yield model is deduced in this thesis. Then a formula is given to show the relationship between yield and reliability, which also includes many factors with respect to design parameters such as the line width and the spacing between the lines and to processing parameters such as the distribution of defect sizes.The lifetime model of interconnect represented in the thesis has a great significance to the evaluation of reliability for 1C. And, it contributes much to the yield prediction to use the calculation method of critical area expressed in this thesis. The quantitative description of reliability and yield makes it possible to estimate circuit's reliability from its yield.