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Design and characterization of RF components for inter and intra-chip wireless communications

Posted on:2001-06-20Degree:Ph.DType:Dissertation
University:University of FloridaCandidate:Kim, KihongFull Text:PDF
GTID:1468390014453051Subject:Engineering
Abstract/Summary:
This dissertation focuses on RF component design and characterization for the wireless clock distribution system. The wireless clock distribution system using integrated antennas has been proposed as an alternative to the conventional clock distribution network using metal interconnects. In the system, receiver and transmitter antennas replace global clock tree and the local clock distribution from the clock receiver is accomplished through conventional clock distribution network such as H-tree and grid. In the system, the clock signal is transmitted at high frequency (>20 GHz), and the clock receiver receives the high frequency clock signal and divide it down to the actual clock frequency (∼2.5 GHz).; A biased n-well inductor is implemented using 0.8-μm CMOS process. The inductor has biased n-well to reduce parasitic capacitance between the metal spiral and the substrate. It is shown that the parasitic capacitance is reduced by a factor of 2 and quality factor is increased by 10%. The parasitic capacitance can be changed by changing the bias to the n-well. 0.6nH inductors are implemented using 0.1-μm CMOS process on SOS and SOI. The quality factor of the inductors are 8 and 6.5 at 12.5 GHz.; 13-GHz tuned amplifier is implemented using 0.1-μm CMOS process on SOS and SOI. These amplifiers are the first in a CMOS technology to have tune frequencies greater than 10 GHz. The transducer gains are 15 dB and 5.3 dB for SOS and SOI amplifiers, respectively. SOS amplifier has noise figure of 7 dB and power consumption of 58 mW. SOI amplifier has noise figure of 9.1 dB and power consumption of 45 mW. The experimental results suggest that design of ∼20 GHz amplifier may be possible.; Integrated antennas are fabricated and experimentally evaluated. Linear, meander, and zigzag dipole, and loop antennas are implemented and characterized. 2-mm long, 30-mm wide, 30-degree zigzag dipole antenna pair on 20 Ωcm silicon substrate show −56 dB gain for 2 cm distance. Loop-zigzag pair shows −60 dB gain for 2 cm distance. Loop antennas with compact size and isotropic radiation pattern are ideal for transmitter antenna for wireless clock distribution system.; This work shows that wireless communication in an area of 2 cm radius is feasible and opens up possibilities to use the components to develop general purpose inter and intra-chip wireless communication systems.
Keywords/Search Tags:Wireless, CMOS process, SOI, SOS
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