| The objective of this research is to investigate the deep submicron CMOS transistor design and reliability by studying the gate oxide integrity. From the electrical point of view, three aspects are covered as following.; It is illustrated that direct tunneling is the dominant field emission process in the ultra-thin gate oxide. Surface roughness is revealed to be a prominent problem when the gate oxide is scaled down to 1.5 nm level. A more meaningful capacitively effective thickness is defined and turns out to be smaller than the geometrically average thickness. An equivalent circuit model including direct tunneling conductance, surface roughness induced conductance, as well as series resistance is proposed in a unified manner.; In high-k gate dielectrics, the tunneling currents are found to be orders of magnitude smaller than that in silicon dioxide with the same equivalent oxide thickness. For a covalent oxide, the barrier height is reduced by MIGS, thus the gate leakage is raised considerably. The high- k augmented threshold voltage roll-off is modeled by a higher order equation. When a thin interlayer of lower-k dielectric is sandwiched between the high-k dielectric and the silicon, an “electrical focusing” picture of the interlayer is proposed to explain the improvement of the threshold voltage roll-off. A new method is developed to evaluate the tunneling current in the stack gate architectures. A design optimization of the stacked layers is subsequently presented.; For ultra-thin gate oxides, the device performance degradation after soft breakdown are exposed. The DCIV method is employed to verify the degradation and compared with other methods. The SRH recombination theory is used to extract the interface states and oxide traps. Oxide stress and channel hot carrier stress are applied to the transistor at the same time to mimic the real circuit operation condition. The extracted parameters before and after the stress are then used to simulate the RF low noise amplifier (LNA). It turns out that S-parameters, gain, noise figures, and linearity are all degraded. The experimental data strongly indicates that the soft breakdown should be considered as a new failure criterion for the next generation CMOS. |
