Gate stack for sub-50nm CMOS devices: Materials, engineering, and modeling

As CMOS technology continues to scale beyond the 100-nm node, many of the materials currently used in CMOS fabrication approach their physical limits. For example, the SiO₂ gate dielectric is now only several molecular layers thick and can no longer serve as a good insulator between the gate and the channel of an MOS transistor. It is expected that new materials such as high-κ dielectrics and metal gate electrodes will have to be used in CMOS fabrication in order to ensure continued scaling of the technology.; High-κ materials have been shown to successfully reduce the tunneling leakage current through the gate dielectrics. However, two important issues related to alternative gate dielectrics still have to be addressed: reliability of these dielectrics and their effect on the mobility of channel carriers. We first examine the reliability of ultra-thin (14 Å equivalent oxide thickness) silicon nitride gate dialectics under both Fowler-Nordheim and hot-carrier stress. The projected lifetime of this dielectric is similar to that of SiO₂ and meets the requirements imposed by device performance. We further attempt to examine the physical mechanisms responsible for the degradation of ultra-thin silicon nitride through modeling of the random telegraph noise observed in the gate leakage current. We then propose a model that explains the degraded carrier mobility in transistors with alternative gate dielectrics, and suggest some possible ways to preserve the high mobility inherent to the Si-SiO₂ interface. The most straightforward way to preserve high channel-carrier mobility is to include a thin layer of SiO₂ between the channel and the high-κ dielectric layer.; It is therefore likely that future gate dielectrics will be comprised of more than one layer. A simple and precise model for direct tunneling through multi-layer gate dielectrics is indispensable for understanding the scaling of such dielectric stacks. According to the tunneling model proposed here, gate leakage current through various gate dielectrics (both single- and multi-layer) as a function of the equivalent oxide thickness of the dielectric stack is confined to a family of universal lines. Each of the lines is defined by a single number, the tunneling attenuation coefficient, which is a simple function of the dielectric's parameters.; Metal gate electrodes can also help CMOS scaling by eliminating the polysilicon gate depletion. NMOS and PMOS devices for most applications require gate electrodes with two different work functions. While several promising candidates have been proposed for either NMOS or PMOS devices, the integration of the metals with two different work functions on a single CMOS wafer remains a critical challenge. Here we propose an attractive way of making dual-work-function metal gate CMOS transistors based on metal interdiffusion. To demonstrate this proposed CMOS process we fabricated metal-interdiffusion-gate FETs with nickel and titanium gates.