Investigation of tungsten gate fully depleted SOI CMOS devices and circuits for ultralow voltage applications

The field of microelectronics is moving in the direction of low voltage, low power and high speed. Silicon-On-Insulator (SOI) technology has drawn serious attention from the dominating bulk silicon Complementary Metal-Oxide-Semiconductor (CMOS) technology with the improved performance at low voltages. Among the family of various SOI structures, fully depleted SOI (FDSOI) technology has been widely explored for the challenging trends of high speed and low power. However, the dependence of threshold voltage on the Si film thickness for dual-poly gate FDSOI devices makes it extremely difficult to have good threshold voltage uniformity with film thickness fluctuations.; This dissertation is concerned with the adoption of midgap tungsten gate and lightly doped channel design for ultra thin FDSOI technology to reduce the threshold voltage dependence on the SOI film thickness and channel doping density. In addition, this approach can set the threshold voltage of both NMOSFETs and PMOSFETs symmetrically at ±0.3V for ultra-low voltage applications.; The successful demonstration of tungsten gate CMOS technology is based on several factors. In particular, there is the need for compatibility with the underlying ultra-thin gate dielectric. In addition, the quality of the Si-SiO₂ interface impacts the mobility and the subthreshold characteristics of the CMOS devices. Tungsten deposited by chemical vapor deposition (CVD) is selected in our study because of its compatibility with ultra-thin gate dielectric. However, the interface in CVD tungsten gate MOS structure exhibits high D_it (≥5 × 1011/cm 2-eV) after the conventional forming gas anneal at various temperatures for different periods of time. This work, for the first time, provides solutions to reduce D_it in the CVD tungsten gate MOS devices, which translate to the improvement in carrier mobility and subthreshold slope of tungsten gate MOS field effect transistors (MOSFETs).; Both dual poly silicon gate and tungsten gate processes have been developed and executed for the fabrication of FDSOI CMOS devices and circuits. The polysilicon gate FDSOI CMOS devices and circuits are characterized in detail to gain an understanding of critical processing issues and device physics. Poly gate depletion effects are observed from high frequency C-V measurements and are taken into account in the device model to extract the gate oxide thickness. A capacitance network model is used to characterize the subthreshold slope in short channel devices. This model is also used to reexamine the classical substrate bias effect on the threshold voltage for ultra thin FDSOI devices, where the carrier is no longer confined within a negligible distance to the front surface. The performance of FDSOI CMOS circuits has been characterized using 101 stage NAND gate ring oscillators with channel length 0.25μm and 0.12μm. The success in operating the ring oscillator circuit at 0.25V supply voltage is due to the very symmetrical NMOS and PMOS I-V characteristics with a 103 on-off current ratio at 0.25V gate bias. A figure of merit, the product of propagation delay and power dissipation, of 5fJ is obtained at 0.25V supply voltage on 0.25μm ring oscillators. The speed performance of ring oscillators is expected to improve with reductions in the load capacitance and series resistance.