Gate-stack and channel engineering for advanced CMOS technology

CMOS device scaling has been the primary means by which significant gains in circuit performance and density are achieved for the past few decades. Significant difficulties in device scaling are faced in recent years and the challenges are related to limitations in material properties and front end process technologies. These technological barriers have to be overcome in order for the full potential of bulk planar CMOS technology to be realized. This dissertation work explores the most important front end process and material challenges faced in device scaling. This work also investigates an alternative device structure, the ultra-thin body transistor, for device scaling beyond the limits of the bulk transistor structure.; Chapter 1 reviews the current issues in device scaling and provides the motivation for this work. Chapter 2 investigates several alternative gate dielectrics for replacement of the conventional SiO2 gate dielectric. The most promising Si3N4-based gate dielectric technologies were evaluated experimentally using a 0.1 mum CMOS process. A direct tunneling model was employed to study the gate leakage characteristics of alternative gate dielectrics such as Si3N4, Al2O 3, and HfO2, providing guidelines for the selection of gate dielectrics based on projected technological requirements. Chapter 3 explores the introduction of metal gate electrodes to replace the dual-doped poly-Si gate electrodes in order to eliminate problems such as gate depletion and gate dopant penetration into the channel. A dual metal gate process was developed. The interface between a metal electrode and alternative gate dielectrics was studied, showing the existence of an interfacial dipole layer. The effect of this interface dipole layer on the selection of gate electrode materials for optimal device performance was highlighted. Chapter 4 explores a way to utilize strain-induced band structure modification to enhance carrier mobility in a MOSFET channel. A compressive strained SiGe channel was realized using a novel process design, leading to significant drive current enhancements. Chapter 5 implements the concept of an ultra-thin body silicon-on-insulator (SOI) MOSFET. A novel solid-phase epitaxy technique and a compressive strained SiGe channel were incorporated. The major conclusions are consolidated in Chapter 6.