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Advanced gate materials and processes for sub-70 nm CMOS technology

Posted on:2003-10-03Degree:Ph.DType:Dissertation
University:University of California, BerkeleyCandidate:Ranade, Pushkar SharadFull Text:PDF
GTID:1468390011988911Subject:Engineering
Abstract/Summary:
The continued evolution of CMOS technology beyond the 90 nm technology node will most likely be driven by advances in materials engineering and process integration. Fundamental changes in the materials used in the MOSFET gate stack will become necessary as will novel processing techniques and device structures. These in turn will introduce new process integration challenges. This work addresses two such challenges.; It is generally believed that the performance of deep-sub-micron CMOS transistors can be improved through the use of metal gate electrodes instead of the conventional polycrystalline silicon electrodes. A major challenge in the introduction of metal gate electrodes is the need to obtain distinct gate work functions for NMOS and PMOS devices. While two metals would ordinarily need to be used on a single silicon substrate, a method that allows the metal gate work function to be tuned over the required range is highly desirable. In this work, a general framework for metal gate work function engineering is developed and the application of such techniques to advanced transistor fabrication is discussed.; The fabrication of ultra-shallow junctions in the source and drain regions of a transistor presents another significant process integration challenge. This task is more challenging for PMOSFET fabrication, given the low solid solubility and high diffusivity of boron in silicon. A novel approach for fabricating ultra-shallow and abrupt p+/n junctions is described. Selective germanium deposition on active silicon regions is used to create an elevated source/drain structure. The implantation of boron into germanium and the subsequent co-diffusion of germanium and boron into the silicon substrate is used to confine the B atoms to a shallow region under the substrate surface and form extensions to the gate electrode. Sub-70 nm elevated source/drain bulk silicon PMOSFET devices have been fabricated to demonstrate the effectiveness of this approach.
Keywords/Search Tags:Gate, CMOS, Silicon, Process, Materials
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