Solving complex modeling of system-on-a-chip (SOC) test automation and optimal resource allocation by neural networks

In this research, we investigate the methods for solving the complex modeling of System-on-a-Chip (SOC) test automation. In the semiconductor industry, a new system design, called System-on-a-Chip (SOC) design, is currently being introduced to use multiple embedded modules built on a single chip. With today's technology, a single chip can consist of millions of transistors or components. To design a SOC system on a single chip, a designer often uses pre-designed, reusable megacells known as cores in the SOC design. Embedded the cores onto SOC increases width of the system bus and thus increases overall system performance, i.e., it can offer higher speed and lower power consumption on SOC chips.; The objective of this research is to optimize the testing time and the test resource allocation for System-on-a-Chip (SOC). The mathematic formulation and the neural networks with different techniques are proposed to solve these SOC test problems. The objective of this SOC test automation is to minimize the SOC testing time subject to different constraints: (i) precedence constraint, (ii) test resource constraint, (iii) core constraint, and (iv) power constraint. Heuristic algorithms are used to help the neural network avoid getting trapped in a local optimal. The developed neural networks can effectively solve the SOC test scheduling models with disjunctive constraints. The proposed maximum neural network can be used to solve NP-hard SOC test problems within polynomial time. The results show that it is possible to find the optimal SOC testing time of the complex SOC systems with shorter computation time than the existing traditional methods. The techniques presented in this research can be used in the test automation for System-on-a-Chip (SOC) design.