Extension, benchmarking and statistical application of the PSP MOSFET model

This dissertation describes the development of the industry standard PSP Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) compact model in three steps: the extensions of the model to include doping non-uniformity effect, development and application of benchmark tests, and statistical application of the model.;The first part of the dissertation presents the compact modeling techniques required to account for the vertical and lateral doping non-uniformity stemming from the channel impurity profile optimization in state-of-the-art MOS transistors. These include bias dependent body effect factors and separate effective impurity profiles for modeling I-V and C-V characteristics of MOSFETs with halo/pocket implants. A new modeling approach based on a voltage transformation technique is developed within the context of the PSP model but is compatible with any surface-potential-based model. This newly developed model is verified by comparison with experimental data from two advanced complementary metal-oxide-semiconductor (CMOS) processes and with two-dimensional numerical simulations.;To ensure physical qualitative behaviors of compact models of MOS transistors in terms of the drain current, terminal charges and their derivatives, several "benchmark tests" were developed over time. With the rapid spread of the radio frequency (RF) CMOS technology, the requirements imposed on qualitative behavior of MOSFET compact models are becoming ever more stringent. Several new benchmark tests were developed to assure that transistor characteristics predicted by compact models satisfy the needs of the circuit designers. Chapter 4 presents a survey of both the traditional and newly developed benchmark tests with applications to the PSP model.;PSP and the Backward Propagation of Variance (BPV) method are used to characterize the statistical variations of MOSFETs. The third part of the dissertation introduces two developments of this technique. First, the BPV formulation is extended to include modeling of inter-device correlations of electrical performances. Second, BPV statistical modeling of NMOS and PMOS devices is, for the first time, coupled by including self-consistent modeling of ring oscillator gate delays. The proposed techniques are validated using Monte Carlo simulations and by comparison to experimental data from various CMOS technologies.