Process-based compact modeling and analysis of silicon-on-insulator CMOS devices and circuits, including double-gate MOSFETs

The main topic of this dissertation is process-based modeling of scaled silicon-on-insulator (SOI) complementary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs), including double-gate (DG) MOSFETs. The University of Florida SOI (UFSOI) fully depleted (FD) and partially depleted (or non-fully depleted, NFD) SOI MOSFET compact models are refined and upgraded in order to apply them in simulations of scaled SOI CMOS devices and circuits. For DG MOSFETs, the first version of the University of Florida DG (UFDG) compact model is developed.; As CMOS technologies are being scaled down to deep sub-micron dimensions, more and more previously unimportant physical phenomena in the shrinking MOSFETs are becoming significant. Polysilicon-gate depletion and carrier-energy quantization, both of which reduce the drive current and the effective gate capacitance, are now important, and hence they are incorporated in the UFSOI models to assure accuracy of scaled device and circuit simulations. The UFSOI models are process-based, and hence their calibration must be done properly to ensure their reliability. To obtain a set of unequivocal model parameters, reflecting the process information and underlying physics of SOI MOSFETs, a process-based model-calibration methodology, which is simple and systematic, is developed and demonstrated for both FD and NFD devices.; We further apply UFSOI to gain insight into the behavior of SOI MOSFETs in integrated circuits via the physical nature of the model. A physics-based study of floating-body (FB) effects on the operation of SOI DRAM is done. Design insight regarding dynamic retention time and sensing is provided. However, due to the history-dependent FB effects in SOI CMOS circuits, comprehensive and intensive simulations are usually necessary. Hence, approximate analytical derivatives, needed for the Newton-Raphson-based nodal analysis in circuit simulation, are incorporated in UFSOI in order to reduce the run time for simulation-based study of the hysteresis.; Although SOI CMOS performance is superior to that of the bulk-silicon counterpart, its scalability is no better. A revolutionary approach to continuously exploit advantages of SOI without the worrisome FB effects is aimed at technologies like extremely scaled DG CMOS, which is evolved from FD/SOI. To extend the capability of UFSOI/FD for general DG application, a new process-based UFDG model is developed. The UFDG model is generic, enabling the evaluation of different DG structures and technologies at the circuit level. The model is demonstrated in comparisons of symmetrical- and asymmetrical-gate DG MOSFETs involving device and circuit simulations.