| The enormous advances in process technology over the past decade has enabled reconfigurable devices to be attractive for a wide spectrum of applications compared with conventional fabrics such as microprocessors, DSPs, and ASICs. The unique capability of reconfigurable devices for post-fabrication and application-specific hardware customization has the potential to deliver ASIC-like performance with microprocessor like flexibility. However, application development for reconfigurable devices has been dominated by the conventional ASIC design flow that prevents them from achieving their full potential; reconfigurable devices are treated only as programmable devices while hardware reconfiguration is not considered as part of application execution. This dissertation addresses the fundamental challenges in mapping applications onto reconfigurable hardware based on run-time parameters.;A novel approach is proposed that is based on algorithm-specific and instance-aware hardware reconfiguration. Initially, based on the semantics of a given algorithm and the target reconfigurable device, algorithm-specific configurations are derived off-line. Then, based on these algorithm-specific configurations, instance-aware reconfiguration occurs to adapt the hardware to the given run-time parameters. The performance metric is the effective execution time. This consists of the time required to map the application onto hardware and the time required to execute the application on hardware. The objective is to dramatically reduce the contribution of the mapping time to the effective execution time to improve the overall performance.;Using the proposed approach, significant performance improvements are achieved for a wide range of applications compared with the state-of-the-art. The applications of interest include private-key cryptography for Internet security, graph problems, matrix arithmetic operations, and boolean satisfiability. Known solutions for these applications either focus on improving only the execution time on reconfigurable hardware ignoring the mapping time or fail to explore run-time hardware reconfiguration to improve the overall performance.;To enhance the feasibility of our approach in embedded environments and to enable multi-personality FPGA-based embedded products, a configuration compression technique is developed that minimizes the memory requirements for storing configuration data. Such a compression approach is essential to cope with the tremendous growth in the size of configuration bit-streams. Our approach requires minimal decompression hardware and does not affect the time required to configure a reconfigurable device. Experimental results demonstrate that near-optimal compression ratios can be achieved for configuration bit-streams of real-world applications. |
