Research Of Some Important Problems For Dynamical Reconfigurable System

With the rapid increase of the computing requirement from some applications such as communication and multimedia technologies, the performance improvement of traditional processors and ASICs has been required greatly. Due to the advancement of the VLSI technology and the reconfigurable hardware such as FPGA, the reconfigurable computing has become an important resolution for these kinds of applications, especially the advent of the partially run-time reconfigurable ability of reconfigurable hardware. But, it is very difficulty for reconfigurable computing to become actual universal and high performance computing system with the current reconfigurable hardware architecture and reconfiguration technology. Based on the dynamical reconfigurable system composed of the microprocessor and reconfigurable hardware, some important issues have been studied in this dissertation. For example, the reconfiguration schemes, the management of reconfigurable resources, the scheduling and placement of hardware task and the hardware/software partitioning. Some solutions are proposed and the experiment results are analyzed. The results show that they are benefit for the reconfigurable computing and its practicality. All of the researches are as follows.Based on the analysis of the configuration architecture of FPGA and the structure of partial bitstream for dynamical module, the Dynamical Module ReLocation method (DMRL) is implemented. Module based partial reconfiguration is efficient for decreasing the reconfiguration overhead. The partial bitstream was generated on some area of FPGA in advance. So this dynamical module won't be configured rightly when its original area has been occupied by another running module. The dynamical module can be shifted to another empty area on the homogeneous resource using DMRL method. And the execution efficiency of the reconfigurable system will be improved.The configuration page based reconfigurable resource management is proposed and the prototype system is implemented on the Virtex II platform FPGA. The different reconfigurable resource is modeled respectively and organized by the configuration page. And the size of the configuration page is discussed. Different number of continuous configuration pages can be allocated to a hardware task at run time. Unused configuration pages can be reclaimed and some neighboring configuration pages can be merged. The reconfigurable resource management is implemented effectively in one-dimensional area model.A two-dimensional area model of reconfigurable hardware is proposed in this dissertation. The reconfigurable resource management and the hardware task placement are presented based on the two-dimensional area model. The unoccupied resources on the reconfigurable hardware can be effectively managed by the Task-Top based Keep All Maximal Empty Rectangles algorithm. It facilities the dynamical allocation and reclamation of the reconfigurable resource, and the FF and heuristic BF algorithms to select a Maximal Empty Rectangle to place hardware task at run time. Compared to the one-dimensional area model, the utilization per cent of reconfigurable hardware is improved, and so the system performance.Based on the two-dimensional area model of the partially dynamical reconfigurable hardware, the hardware/software partitioning for the dynamical reconfigurable system is implemented by the genetic algorithm and hill-climb algorithm, where the configuration delay and parallel execution of hardware tasks are considered. And the partitioning results are evaluated by the dynamical priority scheduling algorithm. The application presented by the task flow graph can be scheduled to the microprocessor and reconfigurable hardware effectively using the partitioning algorithm. The results show that the partitioning algorithm is helpful for them to cooperate with each other and improve their performance.