A 900 MHz dual conversion, low-IF CMOS GSM receiver

This dissertation reports on a highly integrated low power, 900 MHz GSM receiver realized in 0.35 μm CMOS process. The receiver uses a dual conversion to low-IF architecture to lower the impact of the baseband noise. The receiver achieves channel selection, image rejection and more than 100 dB controllable gain. The receiver alone consumes 22mA from a 2.5 V power supply and has a noise figure of 5 dB at minimum detectable signal and input IP3 of −16 dBm. The VCO meets the GSM phase noise requirements at all frequencies including the 3 MHz offset by some margin.; This dissertation identifies various problems in implementing a highly integrated, low power CMOS GSM receiver. The appropriate architecture is then proposed. Design issues of various blocks including LNA, mixers, PGA, VCO and passive and active polyphase filters are discussed. Measurements and simulation results verify the design choices.