| The rapid increase in the demand for broadband data communication systems has motivated extensive research on higher-speed, higher-integrated solutions with lower cost and lower power consumption. This research deals with architecture and circuit design as well as theoretical modeling for such applications.; First, we propose an analysis of regenerative dividers that predicts the required phase shift or selectivity for proper operation. A divider topology is introduced that employs resonance techniques by means of on-chip spiral inductors to tune out the device capacitances. Configured as two cascaded ÷2 stages, the circuit achieves a frequency range of 2.3 GHz at 40 GHz while consuming 31 mW from a 2.5-V supply.; Next, we present a 40-Gb/s phase-locked clock and data recovery circuit incorporating a multiphase LC oscillator and a quarter-rate bang-bang phase detector. The oscillator is based on differential excitation of a closed-loop transmission line at evenly-spaced points, providing half-quadrature phases. The phase detector employs eight flipflops to sample the input every 12.5 ps, detecting data transitions while retiming and demultiplexing the data into four 10-Gb/s outputs. Fabricated in 0.18-mum CMOS technology, the circuit produces a clock jitter of 0.9 psrms and 9.67 pspp with a PRBS of 2 31 - 1 while consuming 144 mW from a 2-V supply.; Finally, a large-signal piecewise-linear model is proposed for bang-bang phase detectors that predicts such characteristics of clock and data recovery circuits as jitter transfer, jitter tolerance, jitter generation, bit error rate, and capture range. The results are validated by 1-Gb/s and 10-Gb/s CMOS prototypes using an Alexander phase detector and an LC oscillator. |
