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The Design Of Charge-pump Phase-frequency Detector Circuit

Posted on:2011-05-21Degree:MasterType:Thesis
Country:ChinaCandidate:L ZouFull Text:PDF
GTID:2178360305973026Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
As one of the important part of integrated circuit, phase-locked loops have been widely used in the network communication and the system clock. Charge pump phase-locked loop (CPPLL) with small lock and large scope captures advantages become the mainstream of PLL products. As a key component of phase-locked loop, phase detector and charge pump (CP) design has become a hot spot in the modern communications and Radio Frequency (RF) fields study.This paper has shown a design of charge-pump phase-frequency detector (PFD) for high quality performance, and gives the whole frame schematic diagram. It firstly shows development process of CPPLL, its work principle, types and performances. Detailed instructions of performance and design requirements of PFD and CP have also been given. The circuit design diagram contains PFD, CP, offset voltages, reset circuit and buffer circuit.Based on common edge-triggered flip-flop, this paper presents a differential PFD of SCL(Source Coupled FET Logic) structure, which structure is simple. It has characteristics of high working speed and low power consumption. But disadvantages of PFD reset circuit delay increase must be considered which will affect the entire PFD circuit performance. In addition, this paper also given a kind of current source with charge-discharge all differential charge pump design based on the normal charge pump basis. It has advantages of low static power, excellent linearity, good current matched performance and high speed. Through the simulation analysis, we know the mismatch current of current sources with charge-discharge all differential charge-pump volume is lower than ordinary charge-pump. All design work is based on Chartered 0.35um CMOS process technology. Circuit simulation and analysis of this PFD has been done on Mentor Graphics ELDO software platform.The requirements for layout design of analog integrated circuit have been given. This paper also analyzes a few problems emerged in layout and optimization. Finally, PFD circuit which meets the requirement has been realized.
Keywords/Search Tags:PLL, PFD, CP, SCL, current mismatch, reset circuit
PDF Full Text Request
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