Analysis and modeling of parasitic effects in advanced silicon-on-insulator CMOS technologies, including nonclassical ultra-thin-body transistors

This dissertation mainly focuses on analysis and modeling of parasitic effects in advanced silicon-on-insulator (SOI) complementary metal-oxide-semiconductor (CMOS) technology. As the channel length is reduced to the nanometer regime, the suppression of parasitic effects becomes an increasingly difficult technological challenge. First, the direct gate tunneling current is a major parasitic leakage component because extremely thin gate oxide is required in order to provide sufficient current drive with reduced supply voltage, and to control short-channel effects (SCEs). Gate-to-body tunneling current, which modulates the body voltage in scaled partially depleted (PD) SOI MOS field-effect transistors (FETs), is physically modeled and implemented in the University of Florida PD SOI/Bulk (UFPDB) MOSFET model. Several scaling effects (i.e., quantization effect in the channel, exchange energy of inversion electrons, and Fermi-Dirac statistics in the high-doped gate) are identified and accounted for. Using the model in UFPDB, it is shown how the tunneling current tends to suppress dynamic floating-body effects in some PD SOI circuits, providing benefits that follow from the complex interactions among the bias conditions, circuit topologies, and switching patterns. The parasitic bipolar-junction-transistor (BJT) effects in the floating-body SOI MOSFET are modeled because they can induce transient BJT current and amplify the gate-induced-drain-leakage (GIDL) current in nonclassical devices. The previous version of the BJT model in the University of Florida double-gate (UFDG) MOSFET model is modified and upgraded to describe correctly the majority-carrier concentration, which governs the parasitic BJT gain, in the (undoped) ultra-thin body (UTB) of nonclassical MOSFETs. The triple-gate MOSFET (TGFET), proposed as a means to alleviate the stringent UTB processing requirements, can be undermined by the top corners of the silicon-fin body, which can significantly affect the channel current-voltage characteristics of the TGFET. It is shown that the corner effects can be eliminated by leaving the body undoped. Then, for viable undoped bodies, the UTB dimensions needed to control SCEs in nanoscale TGFETs are examined by three-dimensional numerical device simulations. The results show that much more stringent body scaling is needed for undoped TGFETs relative to the doped ones, which are technologically and electrically infeasible. When the undoped-body dimensions are scaled for adequate SCE control, it is found that the TGFET suffers from a significant layout-area disadvantage relative to the double-gate (DG) FinFET and the planar fully-depleted MOSFET (FDFET), and thus it is not feasible. It is concluded that the DG FinFET, which is more scalable than the FDFET, is the nonclassical device with the most potential for future nanoscale CMOS applications.