Exploring the Emerging Design and Variability Challenges in Multi-Gate CMOS Devices

Multi-gate CMOS devices (including FinFETs) exhibit superior gate control over the channel region and near-ideal subthreshold characteristics, leading to more energy-efficient circuits and systems. As recently announced by Intel, for the first time in the history of modern electronics, a "non-planar" 3-D device (FinFET) is going to replace the planar CMOS devices for sub-22 nm technology nodes. These 3-D device structures usher several paradigm shifts in the circuit design arena and also require understanding of new static and dynamic variability phenomena to optimize the designs and thereby extract the maximum advantages. In this dissertation, we address some of the key design and variability challenges in multi-gate CMOS devices and circuits.;More specifically, we illustrate an accurate estimation method to quantify the effect of width quantization on the power consumption of multi-gate devices and circuits. Width quantization property of multi-gate devices also restricts the design optimization that is normally achieved via continuous device sizing. Hence, a novel dynamic gate (a key component used in memory designs) is introduced, which employs the exclusive property of the FinFET devices (capacitive coupling between front- and back- gates) to simultaneously improve the energy-efficiency as well as reliability. Additionally, the difference between independent-gate biasing in FinFET devices and body-biasing in planar devices is highlighted in the design of SRAM and a new 8-transistor FinFET-SRAM is proposed for ultra low-power memory applications.;In order to explore the new variability challenges in ultra short-channel metal-gate based multi-gate devices, a new physical model is formulated, which captures the essential physics behind the "work-function variation" (which is known to be the dominant source of threshold-voltage fluctuation in metal-gate devices). The new model is proved to be much more accurate than all existing models in the literature and can be easily employed for analyzing the reliability and performance of multi-gate circuits and systems. Moreover, the impact of work-function variation on the "bias-temperature-instability" characteristics as well as the "quantum threshold-voltage" of multi-gate devices is modeled and quantified. It is shown that these effects will strongly influence the design, performance and reliability of emerging multi-gate CMOS devices and circuits.