Measurement and analysis of variability in CMOS circuits

The scaling of CMOS technology into the deep sub-micron regime has resulted in increased impact of process variability on circuits, to the point where it is considered a major bottleneck to further scaling. In order to continue scaling, there is a need to reduce margins in the design by classifying process variations as systematic or random. In this work, a methodology to characterize variability through measurement and analysis has been developed. Systematic and random, die-to-die (D2D) and within-die (WID) components of variability are quantified and corresponding sources of variability are identified.;This methodology was developed for an early 90nm CMOS process and further refined for an early 45nm CMOS process. Test-chips have been designed to study the effects of layout, and characterize variability of delay and leakage current using an array of test-structures. Delay is obtained through the measurement of ring oscillator frequencies, and transistor leakage current is measured by an on-chip analog-to-digital converter (ADC).;In 90nm, it has been found that transistor performance depends strongly on polysilicon (poly-Si) gate density and that spatial correlation depends on gate orientation and the direction of gate spacing. WID variation is small with three standard deviations over mean (3sigma/mu) ≈ 3.5%, whereas D2D and systematic layout-induced variations are significant, with 3sigma/mu D2D variation of ≈ 15% and a maximum layout-induced frequency shift of 10%.;In 45nm, a process which features immersion lithography, strained-Si and more restrictive design rules for gate spacing, it has been found that systematic layout-induced variability has decreased. However, new sources of variability due to the dependence of stress on layout were found. WID has increased to 3sigma/mu ≈ 6.6% and can be attributed to a smaller transistor area whereas D2D variation has remained at 3sigma/mu ≈ 15%.;This methodology is effective in characterizing variability. It improves the accuracy of statistical models and allows process corners to be set up for WID or D2D variations. In addition, sources of systematic variations are identified and the impact of layout design rules are measured. As scaling continues and variation increases, characterization of variability will become an integral part of the IC design process.