| Three-dimensional integrated circuit (3D IC) technology provides promising benefits for advanced digital system designs. The technology not only helps to overcome the interconnect wire delay barrier by greatly shortening the wire length from a 2D system, but also provides a solution to the well-known memory wall problem by stacking multiple logic and memory dies and connecting them with Through-Silicon-Vias (TSVs). All these features make 3D IC technology an attractive option for the memory intensive integrated system.;Clock distribution is critical to a digital system design. When a system is implemented in 3D technologies, it is more challenging to control the clock skew due to cross-die process variations, high thermal gradients and non-idealities of TSVs. Previous de-skew techniques for 2D ICs, like delay-buffer insertion and active de-skew, introduce large overhead, require complicated analysis, and are unable to compensate the clock distribution errors caused by TSVs and cross-die variations in 3D ICs. Recently proposed 3D clock network designs either do not have the capability to handle cross-tier variations, or oversimplify the effects of TSVs. To implement accurate and balanced clock distribution in 3D ICs, a new adaptive clock topology and de-skew technique are needed.;In this work, new technologies are developed to handle the challenges in 3D clock distribution. Firstly, a new 3D clock distribution topology without H-tree structure is proposed to achieve high quality and good cost-efficiency. Secondly, a novel return-signal de-skew method is developed to handle the cross-tier variations and the 3D wiring asymmetry. Thirdly, to achieve de-skew in a single stage of delay buffer, a phase-mixer based tunable-delay-buffer (TDB) circuit is designed that is tunable in 360 degrees and has good tolerance to process, voltage, and temperature (PVT) variations. Based on these techniques, an accurate and highly adaptive clock distribution network can be implemented in 3D integrated systems.;The proposed adaptive clock design technologies were validated in a chip fabricated in the IBM 7RF 180nm CMOS process. Three transmission line based clock paths with different wire lengths (1.5mm, 3mm, and 4.5mm) were created for testing the return-signal de-skew technology. The measurement results show that, at 1GHz clock frequency, the de-skew technology is able to reduce the clock skews from 440ps to 40ps.;In order to evaluate the effectiveness of the proposed adaptive clock design techniques, design case study is performed. Moreover, a design optimization flow based on thermal profiles is developed to minimize the power and area overhead of the TDB insertion and further improves the adaptive clock network.;In addition to the adaptive clock design methodology, this work also includes the development of other tools and techniques to facilitate memory-intensive 3D IC designs. Memory models, a process-design-kit (PDK) and design tools are developed. A memory generator tool is developed based on timing, power models and 3D PDK. An SRAM chip with on-chip access time measurement was also fabricated in a real process and it proves the benefits of 3D integration. |
