The Design And Implementation Of The Process Insensitive Auto-calibration Technology For On-chip Clock Generator

On-chip clock generator is an essential component for system on a single chip(SOC).For different application scenarios, the performance requirements of the on-chip clocks vary in a wide range. For example, the clock frequency required for the micro-control unit is usually very high and the standard of clock jitter is also strict. Therefore, the low power consumption is quite challenging for the above case. In addition, for the wireless sensor network applications, the power supply is provided by the on-chip energy harvesting module. This kind of energy source is much more limited than the typical batteries. So low power design is always considered as the first priority for these applications.In this paper, an auto-calibration scheme for the on-chip clock generator is presented. The clock frequency is designed to be 10.2 k Hz, with the phase noise of-38 d Bc/Hz at 100 Hz and-89 d Bc/Hz at 10 k Hz respectively. The simulated power consumption is 910 n W.Based on the standard UMC 0.18?m CMOS mixed-mode process, three main building blocks including a current reference, a clock generator and a process insensitive calibration circuit are designed. Compared with the conventional current reference, the proposed implementation exhibits much lower power consumption. This is mainly attributed to our proposed novel structure, which stabilizes the node voltage with feedback network instead of using an amplifier which consumes a large proportion of the power. Moreover, the type of the clock generator is relaxation oscillator which can be categorized to the RC oscillator. Compared with the ring oscillator, the advantages include the superior high linearity and process sensitivity and the generated waveform is a typical triangular wave or square wave; while the disadvantage is jitter performance. Furthermore, the noise current filtering technique is adopted in this design. Compared with the traditional voltage threshold triggered technique, our implementation wellsuppresses the noise interference, leading to much better jitter performance. The process calibration circuits are operated by alternatively adjusting the compensating capacitor and autosensing the mismatch between the generated frequency and the reference frequency.From 100 runs of Monte Carlo simulation, the results indicate that: under 1V power supply at the room temperature, the time needed for calibrating the original frequency to reference frequency is ~40 ms. The standard deviation before and after the auto-calibration is 19.1% and 0.31%, respectively. By adjusting the reference frequency and bias current source, the clock frequency ranges from 10 k Hz to 50 k Hz.Regarding the integrated circuits' fabrication process, the absolute mismatch of the integrated capacitor and resistor are as high as 20% within 3?. By employing superior layout skills, the relative mismatch can be reduced to less than 0.1%. High matching of the resistor and capacitor is important. Furthermore, to reduce the noise interference of the core clock generator, a large variety of guard ring structure are applied to address the noise issue. The final core area of the layout is 270?m*360?m.