| Reconfigurable architectures customize the same piece of silicon for multiple applications. While general purpose processors could not meet the high processing requirements of many new applications, traditional custom ASIC dominates the design space. In wireless communication a DSP processor is typically responsible for low data rate signal processing and is coupled with customized silicon to perform the medium and high data rate processing. The main drawback of a custom design is its long and costly design cycle which requires high initial investment. Typically the time-to-market of custom designs are slow and lack flexibility and programmability resulting in frequent design changes and tape-outs for emerging and developing standards. Reconfigurable architectures, on the other hand, are flexible and convenient, factors that could significantly shorten the design cycle of new products and even extend the life cycle of existing technologies. Tracking new standards is simplified to software upgrades which could even be performed on-the-fly.; One of the challenging applications of a reconfigurable architecture is channel coding. Almost any digital communication system benefits from at least one form of Forward Error Correction (FEC) codes. There are four types of coding typically employed in wireless and wired communications: Convolutional, Turbo, Reed-Solomon and LDPC coding. However, multiple variations and configurations of coding algorithms are mandated in different standards. For example, the Turbo code used in W-CDMA standard has a different polynomial, block size, rate and termination scheme from that used in WiMAX. Furthermore, the data rate and performance requirements are not the same. In practice, this translates to having a plurality of coding accelerators for different coding algorithms and configurations which is very common in industry. In traditional approach a separate coprocessor is employed for every FEC algorithm which results in having a number of accelerators for different FEC codes in a multi-standard mobile device. Unfortunately no single coprocessor is programmable enough to cover all existing configurations of even one FEC algorithm mandated in wireless standards. In this work we introduce RECFEC, a REConfigurable engine optimized for FEC algorithms. RECFEC combines the programmability of a DSP processor with the performance of dedicated hardware and is architected to enable effective software implementation of multiple FEC algorithms and swift switching between them. In this research the design of RECFEC architecture is presented and the implementation of four FEC decoders, Viterbi, Turbo, Reed-Solomon and LDPC{09}is{09}explored. Then{09}a reconfigurable DSP processor called M2 is presented and its coupling with RECFEC to a proposed heterogeneous reconfigurable system as a Software Defined Ratio (SDR) platform is studied and case studies are made for implementation of W-LAN and DVB-T on this platform. |
