| This dissertation discusses the design of an analog baseband processor including channel-select filtering with automatic gain control (AGC) for a 5-GHz CMOS WLAN receiver. Basic concepts and specifications of the IEEE 802.11 a standard are reviewed. Coded orthogonal frequency division multiplexing (OFDM), employed in this standard for high data rate capability in multipath environments, degrades signal detection in the receiver due to the high peak-to-average power ratio (PAPR). Statistical simulation shows that RMS detection has the least error variance among several algorithms.;Channel-select filters of the analog baseband processor are implemented as 3rd and 4th order cascaded elliptic lowpass Gm-C filters. The set of filters have been designed and fabricated in a 0.25 mum CMOS process to meet all the specifications under expected process variations.;The AGC part of the analog baseband processor has three variable gain amplifier (VGA) stages. One of them is placed before and the rest after the channel-select filter. A new gain-control algorithm for the OFDM baseband signal is proposed based on analysis of conventional AGC loops. The new AGC algorithm uses switched coarse gain-setting steps followed by an analog open-loop fine gain-setting step to set the final gain of the VGAs. The AGC circuit is implemented in a 0.18 mum CMOS process using newly designed circuits including linear VGAs, RMS detectors, and current-mode computation circuitry. Experimental results show that the new AGC circuit adjusts OFDM short training symbols to the desired level within settling-time requirements. |
