Multimode Baseband Processor Fast Fourier Transform (fft) Accelerator Research And Design

Multi-standard baseband processors,which merge different communication systems into a single platform,currently are considered to be the future direction of wireless communication devices.On the other hand,Fast Fourier Transform(FFT) and its inverse transform(IFFT),as useful tools for digital signal processing,are pervasively used in communication systems,especially in the Orthogonal Frequency Division Multiplex(OFDM) based ones.Thus,for such multi-standard platforms,a multi-mode FFT accelerator with the capability to deal with all these standards is essential to release other processors from complex computation and still maintain power and area efficiency.This research aims at developing a robust reconfigurable FFT accelerator for multi-standard baseband processors.It is targeted for supporting mainstream communication standards,such as IEEE 802.11,IEEE 802.16(WiMAX),DVT-T/H, CMMB.In this thesis,first at algorithm level,various methods to decompose large point FFT are studied,and then,their complexities of VLSI implementation are analysed and compared.What's more,the finite word-length effect of FFT is also study and an optimized data scaling approach is proposed to improve the utilization of word-length. Second,at architecture level,two traditional FFT architectures are studied and compared.Then,based on them,two multi-mode FFT architectures are proposed,one is for high-speed applications and the other is for ultra low-power and low-cost applications.In the former high-speed one,the SDF structure is optimized to improve its maximal frequency and a special partition of the whole pipeline is proposed to reduce its cost for multi-mode capability.In the other ultra low-power and low-cost one,a novel dual-path pipelined shared-memory architecture and an elaborate memory-sharing scheme are proposed to reduce its area and power.Third,at unit level,some optimization design methods are also adopted to further reduce the cost and power for multi-mode capability.Finally,the verification method is introduced and the test results are given.Both of the proposed designs are verified by FPGA and implemented in ASIC.The high-speed one can deal with a variable FFT length from 22 to 213(12 modes in all). Logic synthesis and layout are carried out in SMIC 0.13-μm CMOS process.This design can reach a peak frequency of 400MHz.The core area of it is 2.7mm2 with the power dissipation of 17.85mW at 20MHz by post-layout simulation.The other ultra low-power and low-cost one supports 8192/4096/2048-point FFT with the throughput met DVB-T/H requirement.It is fabricated in SMIC 0.18-μ.m CMOS process.The core area of the chip is 2.83mm2 with the power dissipation of 25.8mW at 20MHz.The Signal-to-Quantization Noise Ratio(SQNR) of an 8192-point FFT by the two designs can reach 53.17dB with input and internal word-length of l0bit and Obit,respectively.