Design And Implementation Of An Interface Of The Baseband Processor's Transmitter Based On 802.11a Protocol

In recent years, wireless local area networks (WLAN) have been a period of rapid growth. The WLAN system that satisfies IEEE Std. 802.11a is successfully commercialized. In particular IEEE 802.11a Wireless LAN systems utilize OFDM for their physical layer specifications. The IEEE Std.802.11a specifies the functions in the physical (PHY) layer of the networks. In physical layer, it define the method that has 6M, 9M, 12M…54M bps data transfer rates with BPSK, QPSK, 16QAM, 64QAM modulation at 5GHz band carrier. The paper is aiming to researching the implementation of the difference high data rate modulation and data flow control of interface as a part of the project of wireless access terminal, it also presents the Software/Hardware co-design and verification of interface controller of physical layer, which accorded with IEEE Std. 802.11a..At first, the paper explores the algorithm, architecture and implementation to the interface of the transmission part of an OFDM baseband processor targeted on its application in IEEE 802.11a systems. A design and hardware implementation of the transmitter processor has been accomplished on Register-Transfer Layer (RTL). The transmission part of the modulator includes channel encoder (convolutional encode), data interleaving, mapping, IFFT module and Pilot insertion. The inverse transformation part such as deinterleaveing, FFT, Pilot removing is also included. The design of interface controller includes hardware and software. The hardware part includes an embedded system based on Altera IP and systematic communication interface. The systematic communication interface is consisted of singlechip and serial ports. The software part mainly includes VHDL code programming of channel coding, interleaving, Pilot insertion, mapping, etc. In additional, the study of the good characters of the ALTERA Company's technology and the popular intelligent way of IP Core planning are also shown in this paper.In the end, simulations for transimission ports functions and timing show a good performance of the processor on the basis of full achievement essence requirement such as differential rate modulation. The good data flow controlling is also achieved at the same time. In addition, enough attention has been given to the optimization of the physical implementation both in the whole architecture and details, which greatly improves the working speed and reduces utilization of chip resources.