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Design And Hardware Implementation Of An OFDM Baseband Processor For IEEE 802.11a Wireless LAN Standard

Posted on:2007-10-08Degree:MasterType:Thesis
Country:ChinaCandidate:L QuFull Text:PDF
GTID:2178360182970763Subject:Electromagnetic field and microwave technology
Abstract/Summary:PDF Full Text Request
Orthogonal frequency division multiplexing (OFDM) is a preferred data modulation technique for achieving high spectral efficiency and combating fading in high data-rate wireless communications. Therefore, the study on OFDM technology has been a very important issue for communication fields in recent years. In particular IEEE 802.11a Wireless LAN systems which utilize OFDM for their physical layer specifications are becoming so attractive due to their spectacular prospects. This thesis aims to explore the algorithm, architecture and implementation of an OFDM baseband processor targeted on its application in IEEE 802.11a systems. A design and hardware implementation of the transmitter processor has been accomplished on Register-Transfer Layer (RTL). Both the back-end simulations for functions and timing and the on-chip verifications show a good performance of the processor. In addition, enough attention has been given to the optimization of the physical implementation both in the whole architecture and details, which greatly improves the working speed and reduces utilization of chip resources.Besides, based on the discussion of the impacts of sampling frequency offset on the performance of OFDM systems, a new sampling frequency synchronization algorithm in frequency domain is proposed and its mathematical analysis is presented. This algorithm has been optimized to make it easy for hardware implementation, which can give a 20% reduction in logic gates and a double speed than the algorithm using least square (LS) method. MATLAB simulations have been conducted on an 802.11a system platform. The simulation results show that this algorithm can work effectively and fulfill the standard requirements both in the additive white Gaussian noise (AWGN) channel and the multi-patch channel. The algorithm has been successfully implemented on an 802.11a FPGA platform as well. On-chip real-time analysis of the algorithm using Xilinx Chipscop Pro demonstrates that this algorithm can work efficiently and effectively as a block of an OFDM baseband receiver processor.
Keywords/Search Tags:OFDM, baseband processor, sampling frequency synchronization, FPGA, 802.11a
PDF Full Text Request
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