Advanced MOSFET structures for deep sub-100nm ULSI

In this dissertation, a novel transistor structure that has multi-parallel silicon pillar channels with surrounding gates is demonstrated. The transistor is composed of multiple parallel pillar channels. Each pillar transistor is a surrounding-gate transistor. While the minimum pattern of a typical planar-type transistor is gate lithography, the minimum feature of the device demonstrated in this dissertation is minimum length of the active pattern. Therefore, the minimum feature of the critical lithography is greatly relaxed in this device. Theoretically, the transistor provides all the superior characteristics of surrounding gate transistors such as improved short-channel effects, increased drain currents, reduced hot-carrier degradation, and ideal subthreshold swing characteristics of 60mV/decade.; In order to fabricate the transistor, both anodization and electrodeposition technologies were used. Anodized Aluminum Oxidization (AAO) coupled with nickel electrodeposition provides a convenient way to form mask rods for silicon pillar etching without the use of high-cost lithography since the pore size of anodized alumina ranges from 5nm to 1mum for most bias conditions. This technology enables 50nm diameter pattern of vertical silicon channels with 2mum lithograph technology. In addition, the self-aligned source/drain technology adopted in this device fabrication provides excellent scaling properties.; One of the limitations of double-gate transistors is discussed. For the double-gate transistors with mid-gap metal gates and low channel doping concentration, it is found that the subthreshold leakage current increases as a channel length decreases. The holes accumulated in the bulk due to impact ionization are mainly responsible for the increased leakage current. The injected holes lower the potential in the bulk, resulting in increased electron injection from the source. This undesirable characteristic of double-gate transistors limits the application of mid-gap gate materials and low channel doping concentrations as the devices are scaled.; Finally, a novel capacitor-less memory structures are studied. The memory cell is composed of an access transistor and a bipolar transistor connecting to each other. The back gate of the access transistor is the n+ junction storage node. The threshold voltage of the access transistor is changed by the potential of the back gate, resulting in current changes in the access transistor. The current difference of the access transistor is detected by the current sense amplifier. (Abstract shortened by UMI.)...