High-performance low-power carbon nanotube FET SRAM with tolerance to metallic CNTS

In this dissertation, an in-depth study of the design of Static Random Access Memory (SRAM) cell using Carbon Nanotube (CNT) technology is presented. Due to their superior transport properties, low voltage bias and improved current density, Carbon Nanotubes have great potential to replace the conventional silicon MOSFET technology. In this study, an 8-transistor CNTFET SRAM cell shows a 3.2X speed-up, 2.9X savings in dynamic energy, and 61X leakage power reduction as compared to a MOSFET SRAM cell of similar size.;Today's CNT technology has fabrication challenges which prevent its wide use in the implementation of systems. One of these challenges is the undesirable growth of metallic CNTs with semiconducting CNTs. In this study, we present two approaches to overcome the metallic CNT challenge to achieve desirable yield for CNT transistors and SRAM cells. The first approach utilizes serially uncorrelated CNTFET to reduce the probability of non-functional transistors. The second approach requires metallic CNT removal processes and form working transistors by having parallel CNTFET array.;Among the process variations diameter/chirality greatly impacts SRAM performance, energy efficiency, noise margin and yield. Novel optimization schemes for CNTFET SRAM cell design are proposed and evaluated. Simulations show that these optimizations can effectively eliminate all cell write failures and improve the overall performance.;In addition, the SRAM cell design is examined at the near-threshold power supply region to greatly reduce energy consumption. On the other hand, Vdd reduction not only exacerbates write and read delays but also leads to more cell failure because of weakened driving capability. Gated power supply and word-line boosting techniques are investigated to overcome cell write failures in CNTFET SRAM cells. Simulation results show that with careful design methodology, the CNTFET SRAM cells are able to be operated at as low as 0.4V with 3.7X performance improvement using gated power supply and word-line boosting techniques with negligible size penalties.