A fully parallel, multi-chip, long constraint length optoelectronic Viterbi decoder: Design, modeling, and analysis

This dissertation presents a multi-chip, fully parallel, high performance optoelectronic Viterbi decoder architecture based on free-space optical interconnects for decoding rate 1/d long constraint length convolutional codes for digital communications applications. The system employs vertical surface emitting laser (VCSEL)/photodetector based smart pixels designed to implement Viterbi decoding functionality to realize a fully distributed Viterbi decoder. High bandwidth optical and electrical interconnects are employed at different levels of the packaging hierarchy to overcome the routing complexity, speed, and interconnect density limitations of building a long constraint length decoder in VLSI by leveraging the advantages of both interconnect technologies. The large number of processing nodes of the Viterbi network are distributed across K chips (K being an integer power of 4) and intra-chip processors are linked together in the form of de-Bruijn networks via high bandwidth electrical interconnects. Inter-chip processors are connected via optical interconnects with a global K-shuffle interconnection pattern realized by an array of lenses and a mirror to emulate the full scale Viterbi network for metric exchange. A solution is derived for mapping the Viterbi network nodes onto a K-shuffle based photonic module for decoding convolutional codes of any constraint length. The traceback process for extracting the decoded sequence is realized using a permutation network based path history management scheme, which involves routing signals through an independent network comprised of a distributed array of high-speed shift registers, switching elements and optical and electrical interconnects interleaved with the metric transmission network. The high bandwidth and high degree of parallelism of optical interconnects enable high traceback recursion rates, facilitating the reduction in latency and memory requirements. The performance in terms of throughput and latency, and cost in terms of chip area, footprint area, volume, and power consumption are estimated by developing a framework based on a system level characterization tool for integrated circuits with 0.18mum process technology. The performance-cost tradeoffs for the decoder are examined using this framework under various design constraints and key parameters affecting both performance and cost are identified. Prototype VCSEL and photodetector arrays are tested and preliminary experiments characterizing the resolution and registration accuracy of lenses are conducted. Results from the analysis in this dissertation suggest that a high speed, fully parallel, long constraint length Viterbi decoder is feasible with dense arrays of free-space optical interconnect based smart pixels coupled together with high quality multi-scale optics. The implementation of the proposed approach described in this dissertation is hoped to provide new opportunities for long constraint length convolutional codes in real time digital communication systems and in many other applications.