Nested digital background calibration of a 12-bit pipelined ADC without an input SHA

Background calibration has been used to improve analog-to-digital converter (ADC) linearity. It compensates for circuit non-idealities and tracks environmental changes adaptively, without interrupting ADC conversion. In a nested digital background calibration architecture, the outputs of a pipelined ADC and an algorithmic ADC, which is calibrated in the foreground and acts as the reference, are compared. The error between the two outputs is used to digitally calibrate the pipelined ADC. This architecture requires an input sample-and-hold amplifier (SHA) so that the two ADCs sample the same input. Unfortunately, this SHA consumes significant power.;To reduce power dissipation, a digital timing compensation algorithm is used to eliminate the need for the input SHA. It overcomes the timing error between the pipelined ADC and the algorithmic ADC so that the pipelined ADC can be properly calibrated. The implementation follows the Farrow structure for efficiency. Specifically, a differentiator of fixed coefficients is used to build an interpolator. One parameter, the estimated timing error, is adjusted to realize an adaptive interpolator with a variable delay. Thus no computation or memory is required to update the filter coefficients. The main criterion in designing the differentiator, its number of taps, is studied. Digital error compensation is also extended to calibrate individual digital-to-analog sub-converter (DASC) levels as well as interstage gain errors.;To demonstrate the concept, a 12-bit, 20-MSample/s pipelined ADC has been designed and fabricated in 0.35-mum CMOS technology. Test results show that the calibrated pipelined ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 70.2 dB, a spurious-free dynamic range (SFDR) of 80.3 dB, and an integral nonlinearity (INL) of 0.75 least significant bit (LSB) at 58 kHz input frequency. The power dissipation is 231 mW from a 3.3-V power supply and is 23 mW less than a previous prototype with the input SHA. The calibration is off-chip and is estimated to dissipate 8 mW, while the timing compensation accounts for 1 mW. The active area is 7.5 mm2.