| As IC technology advances toward gigascale integration (GSI), the performance of an IC chip will be limited by its interconnection capability. The bottlenecks in chip-package interfacing are mainly from thermal-mechanical mismatch, input/output (I/O) communication bandwidth, power distribution, and heat dissipation. Through wafer-level batch processing, novel integrated interconnects can be used to enable GSI packaging with high I/O density, high reliability, and high performance at low cost.; In this research, a set of integrated I/O interconnection and packaging technologies are investigated. MEMS-based sea-of-leads (SoL) compliant interconnects are demonstrated to be promising to eliminate the need for underfill between a Si chip and organic packaging substrate. Wafer-level packaging with the compliant interconnects can largely reduce the impact on the fragile low-k interlevel dielectric (ILD) films. The technology feasibility of the SoL MEMS I/O interconnects is demonstrated by process integration, assembly, and reliability assessment. To achieve the high power dissipation with compact form factor, integrated thermal-fluidic I/O interconnects and CMOS compatible microchannels are developed to enable a prototype on-chip microfluidic heat sink. In addition, highly integrated electrical and optical interconnects based on dual-mode polymer pillars are fabricated, assembled and tested as a potential solution to the I/O bandwidth bottleneck. The resulting integrated I/O interconnection and packaging technologies are compatible with back-end-of-the-line (BEOL) wafer processing and conventional flip-chip assembly. |
