Design issues for interconnection networks in massively parallel processing systems under advanced VLSI and packaging constraints

The design of interconnection networks for massively parallel processing (MPP) systems is inherently responsive to advances in VLSI and packaging technology. Optimizing the cost and performance of interconnection networks under these constraints requires an understanding of how technology trends affect network design tradeoffs at the architectural level. Technology trends expected to exert a major influence on the cost-performance of MPP interconnection networks include "gigascale integration" (GSI) capability at the chip-level (;The research focus of this thesis is to explore how MPP network architecture can be designed to best exploit VLSI and packaging advances. This problem is explored in the context of two primary research contributions. The first major contribution is a new MPP network topology, the offset cube, designed to leverage the three-dimensional packaging advantages of through-wafer optical interconnects without sacrificing the architectural efficiency required in a multicomputer network. High-performance, deadlock-free wormhole routing protocols are developed for the offset cube and evaluated using flit-level network simulation. The second major contribution is an integrated modeling framework for exploring the interaction of architectural features and implementation technology in VLSI communication routers. The framework consists of a hierarchy of models describing router microarchitecture, chip-area requirements, and internal flow-control delays as a function of both architectural and technological parameters. The framework also includes a flit-level network simulator incorporating behavioral models for router architectural features. Using these models, a set of experimental studies was performed to explore router cost-performance tradeoffs under a 0.35-...