Efficient and high quality delay testing for combinational and scan circuits

The purpose of delay testing is to ascertain correct operation of digital logic circuits at specified clock rates. Two most commonly used delay fault models are considered in this thesis, namely the path delay fault model and the transition fault model.; The path delay fault model is more powerful and realistic. However there are usually a large number of paths in a circuit, which makes it difficult to handle all of them. One way to reduce the cost of test generation for path delay faults is to identify most of the untestable paths before test generation. So they are not targeted during test generation. We propose some new techniques to improve the run time and reduce the memory requirement of the untestable path identification process. After that a novel concept called state tuple is proposed to facilitate test generation for path delay faults. State tuple representations significantly simplify the implementation of robust test generation and provide an easy way to extend an existing test generation system. Even though these techniques help to reduce the run time of test generation for path delay faults, it is still impractical to test all paths in a circuit. One way to overcome this problem is to select a set of paths such that every line in the circuit is covered by at least one of the longest testable paths that contain it (if there are any). Using our research on untestable path identification, several efficient techniques are developed to find a minimal set of paths to achieve this objective.; Due to the prohibitively large number of paths in a typical circuit transition faults are often used to model delay defects in large industrial designs. Conventional transition fault tests can activate and propagate target faults through any paths. Therefore delay defects with small sizes may not be detected if short paths are used for fault activation and propagation. We propose new techniques to improve the quality of transition fault tests. These techniques maximize the delays of paths used for activating faults and propagating fault effects.