| A design of monolithic WLAN transceiver for dual-band multi-standard application is presented in a 0.18um CMOS process with on-chip spiral inductors and 6-metal layers. The transceiver is targeting for IEEE 802.11 a/b/g wireless LAN standards in dual frequency bands. Direct conversion architecture is applied. The transceiver chip contains low noise amplifier, mixer, power amplifier and bandgap reference circuit. Sub-harmonic mixer is introduced in order to reduce DC offset impact in homodyne architecture and, in the meantime, relieve the frequency requirement for LO signal. A new circuit model of Class-A power amplifier is presented to address the problem of determining the optimal load resistance in fully-integrated PA design. Furthermore, a curvature-compensated CMOS bandgap reference is introduced to provide DC bias for transceiver circuits. And a new ESD-sensitive RFIC design methodology is presented to achieve ESD+RF circuit design optimization. |
