Design Of The CMOS Quadrature Modulator And Demodulator For Multi-Mode Multi-Band Transceiver

With the development of the wireless Communication technology, it's application has come into Local Area Network and Automatic Identification. Diversity applications lead to different kinds of communication standards and protocol. It is very practical to develop the Multi-mode Multi-frequency transceiver, which can adapt different kinds of communication standards. Direct-conversion architecture is the best choice for the Multi-mode transceiver, because of it's simplicity and easy to integration. In sub-micro process, however, it's challenge to design the CMOS quadrature demodulator the in low supply voltage and fullfill the requirement of conversion gain, noise figure and linearity at the same time. The main achievements of this dissertation as as follows:(1) After study of sufficient papers on Multi-mode transceiver and detailed analysis of the GSM, TD-SCDMA, WLAN and RFID, standards, the specifications of the modulator and demodulator are proposed and direct-conversion architecture are chosen for the Multi-mode transceiver design.(2) Detailed analysis of main specifications such as conversion gain, noise figure and linearity of modulator and demodulator are presented in this dissertation. An integrated CMOS broadband direct-conversion quadrature demodulator with on-chip LO quadrature phase generator is proposed in this passage. The mixer consists of three stages. The chip was fabricated in Grace 0.18-μm CMOS technology. From 800 MHz to 2.1 GHz, the demodulator achieves 13 dB of conversion voltage gain with 2MHz IF bandwidth, a double-sideband NF of 13.5 dB with 300kHz 1/f-noise corner. The IIP3 is+7 dBm for a 1-MHz IF frequency.(3) Design of 5-6GHz modulator and demodulator for WLAN 802.11a standard is presented in this paper. The two chips are through design, layout work and fabricated in 0.13um RF-CMOS process. On wafer test were finished and measurement results show:for the narrow-band 5.75GHz modulator, the conversion gain is greater than 3dB, the Output P1dB is not less than-1dBm. For the narrow-band 5.25GHz demodulator, the conversion gain is greater than 3dB, and the input third-order intercept point IIP3 is greater than 9dBm;(4) The summary of RF circuit layout is also presented and the discussion of the impact of the signal flow on the RF circuit performance are given in this dissertation.