A study in low-power wireless transceiver architectures in submicron CMOS technology

Wireless radio transceiver design has experienced tremendous advances in the past few years. This is mainly attributed to the emergence of a large number of applications for wireless communications, as well as the rapid advancements in fabrication technologies. The designers' aim is always for a simpler, more compact, less power hungry transceiver architecture. To achieve these goals, most of the transceiver building blocks should be integrated within the transceiver chip, with as minimum number of off-chip components as possible. In addition, a suitable transceiver topology that renders itself easily for integration should be adopted. Furthermore, an implementation technology that can readily accommodate mixed signal integration at a smaller form factor, less power dissipation and lower price is desired.; In an attempt to address the above mentioned challenges in wireless transceiver design, this research presents a study towards the implementation of a simple, low-power and compact full transmit path based on Q-enhanced techniques, using one of the leading technologies in wireless transceiver design, namely, CMOS technology. A transmitter structure, based on the well-known direct conversion architecture, is proposed. Within the proposed structure, the frequency synthesizer is based on Subharmonic Injection Locking technique, using a low-power, low-frequency clock PLL as an injection source. This is intended as a replacement for the usual high power RF PLL used for tuning the transmitter to different channels. A theoretical analysis of subharmonic injection locking using a periodic square waveform as an injection source is performed. Voltage controlled oscillators, with different centre frequencies, are implemented to validate the derived formulas predicting the locking bandwidths using subharmonic injection. Using direct digital frequency tuning of the oscillator's centre frequency, the local oscillator pulling "LO pulling" by the strong power amplifier output, a well-known problem in direct conversion transmitter architectures, is alleviated without the need of any additional circuitry.; The proposed transmitter structure relies on the sharing of circuits between the receiver and the transmitter to save silicon area as well as required power. To this end, a Q-enhanced LC filter used in the receive chain as a band select filter is reused in the transmit chain as a local oscillator. This prompted a detailed study into the structure of these filters, the possibility of fully integrating them, their power consumption, and their tuning algorithms. Important practical considerations surrounding the implementation of high frequency Q-enhanced LC filters in 0.18mum silicon CMOS process are investigated, including realizing the necessary on-chip spiral inductors and Q-enhancement circuits, predicting frequency and Q tolerances and temperature stability, and developing real-time direct digital frequency and Q tuning mechanisms. A prototype filter intended for the 5-GHz band of communications is designed to validate theoretical predictions. The promising experimental results obtained for the implemented prototype illustrate that Q-enhanced LC filters can play an important role in the development of future integrated transceiver products.