Research And Design Of OFDM UWB Transceiver With Full Chip Implementation

Driven by increasing demand of short-range and high-data-rate wireless communications, ultra-wideband (UWB) technology with target data rates up to 480Mb/s even higher within 10-meter distance becomes more and more attractive and is regard as a new poineer technology in future. In this dissertation, the design and integration of a single-chip CMOS transceiver for Multi-Band OFDM (MB-OFDM) UWB system covering the first 3 frequency bands from 3.1 GHz to 4.8 GHz is presented.Firstly, from the system point of view, the RF transceiver based on direct-conversion architecture is proposed with the considering of MB-OFDM UWB application. Together, the technique solutions are proposed to the problems as second-order intermodulation distortion, I/Q mismatch, DC-offset and carrier leakage that resulte from direct-conversion architecture. With the requirements of MB-OFDM proposal, the system design parameters for receiver, transmitter and frequency synthesizer is caculated and discuessed. Based on this parameters, the detailed specifications for the building blocks are derived and verified.In the working band from 3.1 GHz to 4.8 GHz, to keep stable modulation in transmitter chain and stable de-modulation in receiver is difficult for circuit design. So at the transmitter path, we take the the load resonance frequency of mixer several hundreds MHz lower than the load resonance frequency of the programmable gain amplifier, this two resonace frequency points make the whole transmitter gain flat. To prevent the carrier leakage caused by DC-offset, the 7-bits DAC is inserted to cancel this dc-offset. To address the low voltage high linearity requirements of the transmitter path, the resistor feedback transconductance and current mirror techniques are used to convert the input voltage to current. For the receiver front-end, the dissertation proposed a resistor feedback LNA with current reuse input stage and gate inductor. The gate inductor is used for high frequency gain peaking as well as high frequency input matching correction. Under certain gain and NF requirements, this proposed LNA can lower current consumtion with current resuse technique and chip area for the small gate indutor. The LNA and mixer are co-designed with ESD PAD and bonding inductor.Design of the other building blocks in the fully-integrated transceiver, namely synthesizer, LPF ,VGA , are also briefly introduced. Then the key problems like layout plan, on chip RF isolation techniques are carefully considered and the fully-integrated transceiver is finally realized with Jazz 0.18RF CMOS technology. The test results satisfy the system requirements.