Timing Error Tolerance Processor Research Based On Error Detection And Correction

Traditional processor circuit design introduces large amount of static design margins to ensure safety and robustness of processor under variations from process,voltage and temperature(PVT).Timing error tolerance processor uses error detection and correction(EDAC)techniques to fix timing error dynamically to remove static circuit margin and maintain stability at the same time.In this dissertation,we propose several novel EDAC techniques to improve the performance of error correction and area overhead introduced by EDAC circuit.The main contributions of this thesis are described in three aspects as follows.1.High-performance timing error correction technique based on time borrowing.To resolve the CPI(cycle per instruction)performance loss in error correction scheme,a high-performance in-filed error correction technique is proposed,based on time-borrowing.On the detection of a timing error,the timing error latch and data correction latch records timing error and correction input value separately,and then the register output is corrected through a multiplexer without additional clock cycle loss.The in-filed error correction technique resolves the performance loss problem in traditional methods and improves tolerance ability of timing error in processor.2.Timing error mask technique based on ultra-lightweight EDAC.Area overhead is a main bottleneck of the development in EDAC.This thesis proposes an ultra-lightweight error mask flip-flop(EMFF)design using the error detection point to correct timing error directly through a well-designed circuit and the area overhead of EDAC can be significantly reduced.This design can effectively resolve the area overhead problem and improve the energy efficiency of timing error tolerance processor.3.Timing error tolerance design based on error detection and sampling unified(EDSU)technique.By the research of commonality in edge sampling of register and error correction,EDSU is proposed to control the area overhead of timing error tolerance register to an ultra-low level and even negative.This design further explores the possibility of decreasing area overhead in timing error tolerance processor and achieves nearly none performance loss EDAC under lower area cost.Techniques proposed in this thesis significantly reduces performance loss and area overhead in current EDAC research,and effectively expands the tolerance ability of timing error and energy efficiency in processor.